Verilog

Code Verilog

16 bit ALU Verilog design

// 4 channel, 1 bit mux // BK Turley `timescale 1ns/100ps module mux_4to1(out, sel, in0, in1, in2, in3); output out; input [1:0] sel; input in0; input in1; input in2; input in3; reg out; always @( sel or in0 or in1 or in2 or in3) case (sel) 2’b00 : out <= in0; 2’b01 : out <= in1; 2’b10 : out <= in2; 2’b11 : out <= in3; default : out <= in0; endcase endmodule